1. Field of the Invention
The disclosure generally relates to a duty cycle corrector, and more particularly, relates to a duty cycle corrector with a wide adjustable range of duty cycle.
2. Description of the Related Art
In many applications, a clock signal with a 50% duty cycle is important, such as DDR (Double Data Rate) applications and other critical communication applications. A conventional design, for example, uses two differential input clock signals and a differential amplifier to recover a correct output clock signal with a 50% duty cycle. However, in some cases, there is only one input clock signal or a single input terminal, and it is a challenge for a designer to recover a correct output clock signal without using the above differential method. In addition, the conventional differential design may just adjust the duty cycle of a clock signal from about 40% to 60%, which is very limited and may not be applied to some extreme cases.